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Description: 数字频率合成器DDS,具有和单片机接口的直接数字频率合成器的FPGA实现代码(Verilog)-Digital Frequency Synthesizer
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Size: 95232 |
Author: 胡文静 |
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Description: Verilog 实现的DDS源码,可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
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Size: 3072 |
Author: 张松松 |
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Description: 此为Verilog编写DDS时,常用模块,为rom模块。-This is the Verilog write DDS, the common module, the module for the rom.
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Size: 5120 |
Author: name |
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Description: 用verilog写的DDS程序,请用QuartusII 8.1以上版本打开-DDS program written using verilog, please QuartusII 8.1 or later to open
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Size: 1613824 |
Author: 吴恒 |
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Description: 这是一个数字频率综合器(DDS)的Verilog实现源码,采用Quatoues软件综合和仿真-That this is a digital frequency synthesizer (DDS) of the Verilog implementation source code, synthesis and simulation software with Quatoues
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Size: 699392 |
Author: 追月 |
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Description: DDS加法程序,用verilog程序写成,在FPGA的中实现-DDS addition procedures, written with verilog program, implemented in the FPGA' s
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Size: 5120 |
Author: 胡浩 |
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Description: 基于verilog hdl 的DDS设计-The DDS-based design of verilog hdl
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Size: 397312 |
Author: yangyang |
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Description: dds设计,花了一个星期做的,verilog写的,可生成多种波形,频率范围可上M,性能不错。-dds design, spent a week doing, verilog to write, can generate a variety of waveforms, the frequency range available on the M, the performance good.
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Size: 1718272 |
Author: wangmingwei |
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Description: 基于Verilog HDL的迟早门码元同步方案中的DDS程序,已经仿真通过,可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. From HUST.
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Size: 1262592 |
Author: ye |
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Description: 采用verilog实现了DDS发生器,源码已通过仿真编译已经板级调试,可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
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Size: 2048 |
Author: 杨安娜 |
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Description: 基于FPGA的单路DDS函数发生器的实现 ,语言为Verilog-FPGA-based single-channel DDS function generator implementation language for Verilog
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Size: 26933248 |
Author: Filter |
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Description: 本代码采用Altera公司的FPGA为主控芯片,以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz,输出四路频率为70MHz的四相序正弦载波(相位分别为0°、90°、180°、270°)的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真,验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70MHz output frequency of the four four-phase sequence of a sinusoidal carrier (phase were 0 °, 90 °, 180 °, 270 °) design. Using Verilog HDL language for the programming and design with the Quartus Ⅱ of the simulation to verify its correctness.
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Size: 5120 |
Author: biyuming |
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Description: PS/2键盘加DDS的verilog 设计-PS/2 keyboard plus the verilog design DDS
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Size: 1969152 |
Author: 刘汉超 |
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Description: DDS扫频信号源的FPGA实现,有的是verilog编写,欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
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Size: 11176960 |
Author: jin |
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Description: DDS正弦信号发生器verilog的功能强大很实用-dds sin verilog
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Size: 288768 |
Author: 亮晶晶 |
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Description: 用ALTERA 公司的fpga芯片,编程语言是VerilogHDL,实现DDS数字信号发生器,可以产生正弦信号,三角信号,矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
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Size: 1576960 |
Author: 郭晨 |
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Description: 利用dds方法,通过DA输出正弦波,频率1KHz
频率根据代码可调-DA output sine wave frequency 1KHz (Verilog)
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Size: 3603456 |
Author: 范子剑 |
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Description: verilog语言书写的基于DDS相频累加器的正弦波发生器-verilog language of the sine wave generator
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Size: 13312 |
Author: 任健铭 |
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Description: verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
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Size: 425984 |
Author: 陈占田 |
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Description: verilog实现dds,用于FPGA产生正弦波,适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
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Size: 16789504 |
Author: sunlin |
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